This page contains information on a selection of my projects. Click the thumbnails for full scale view. Much more information is available on request.
Thumbnails of Projects, latest first:
- 10GBase-T Architecture
- 1000Base-T Architecture and Layout
- 100Base-TX Architecture
- 100BaseT4 Technology
- Custom Multipliers
- Custom Layout / Library
- Pipelined ADC
- Multiprocessor Architecture
- rRam Multiprocessor
- Adaptive Noise Cancellation
- ARM Microprocessor Chip Development
- Mixed Signal Chip
- Precision Band Gap
- Substrate Regulator
- Special IO Design
- CMOS PLL
- Multi-Valued_logic Chip
10GBase-T Architecture |
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Developed 10Gb Ethernet architecture and simulation for 10G startup and participated in series A fund raising technical due diligence. This included overall architecture and modeling of:
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Developed C++ model of 1000Base-T architecture plus a simulink model.
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Developed detailed model of 100Base-TX architecture plus a simulink model.
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100BaseT4 Innovations |
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While at SMC I proposed a scheme for transmitting 100Mb Ethernet over
Category 3 twisted pair cable. This scheme transmitted data with a 3
level code on 3 wire pairs while listening for a collision on a forth
pair. This arrangement eventually became the ill-fated 100BaseT4
standard. I received a patent for the technology. Text of article. Back to Top
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Working as a contractor I defined the AFE for a 100Base-T2 became
familiar with the DSP architecture.
Also did bench debug of T2 chipset. |
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Per the library (below) I built some custom multipliers based on an
optimized cell library.
These were implemented using Tanner EDA tools and irsim for verification.
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Developed a high efficiency library of schematic / layout cells for fast
implemented of custom DSP macro cells. Shown left is simple LMS filter
tap implemented using the library.
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In 65nm CMOS this bandgap has a precision of ±0.1%.
Responsible for the design, simulation and revue of layout. Back to Top
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Negative Substrate Regulator |
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65nm leakage reduction power supply. A charge pump and linear regulator
provide -0.6V to 0.3V at 8mA.
Responsible for the design, simulation and revue of layout on this project. Back to Top |
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Responsible for a number of IO pad designs, including Crystal
Oscillator, PECL, 5V tolerant, LVTTL etc.
Responsible for the design, simulation and layout on this on many projects. Back to Top |
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In 180nm CMOS this project was for an Ethernet analog front end.
Made from a stack of 1.5 bit switched cap ADC's. The most critical element was the differential stage amplifier shown here. Excellent dynamic characteristics are needed for the system to settle within one clock cycle. A folded structure was used to achieve this within the 1.65V minimum VDD.
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Developed innovative multiprocessor concept, produced software modeling
to test efficiency.
Effort concluded in 2001. However, the performance benefit is so significant that this type of component is bound to evolve eventually. Unfortunately, the hierarchical arbitration scheme was rediscovered and patented by Intel. Back to Top
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Morphosys Multiprocessor Architecture |
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Proposed an innovative re-configurable array processor to DARPA in
conjunction with UCI. Received $1.2M in funding. Personally, I:
A company (Morpho Technologies) was set up to exploit this technology. Back to Top
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Adaptive Noise Cancellation |
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This is a system project to adaptively remove sound noise. My
contribution to this was:
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Mixed Signal Chip with Tanner |
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Shown at the beginning of top level routing this is a mixed signal chip
to interface Cell phones with car stereos through a standard USB cable.
Analog cells included 8 bit ADC, amplifiers, comparators, references, special IO's etc. Not a very complex ship, but all design work done myself.
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During the period 1983-1985 I ran the VLSI Design group at Acorn, later
to become Arm. My contributions included:
More details of my participation.
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A basic CMOS Phase Locked Loop (PLL). One of several I have worked on. This one I own and developed on Tanner.
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A test chip for a JPL/DARPA project to demonstrate features of a "simugate"
4 level logic scheme vs standard binary CMOS logic.
The chip consisted of 4 ALUs, each of 8 bits: 2 implemented in four level logic, 2 implented in binary logic. The custom 4 level logic gates and IO drivers were implemented to tape out within four weeks. |
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